Method and apparatus for testing circuitry with memory and with forcing circuitry

A method and apparatus for testing circuits with memories is provided in which a memory array (26) is coupled to memory input logic (33) and memory output logic (34). Furthermore, forcing circuitry (36) is coupled in parallel with memory (26). An automatic test pattern generator transmits test patte...

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Bibliographic Details
Main Author LO; KWOK YIN
Format Patent
LanguageEnglish
Published 09.12.1997
Edition6
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A method and apparatus for testing circuits with memories is provided in which a memory array (26) is coupled to memory input logic (33) and memory output logic (34). Furthermore, forcing circuitry (36) is coupled in parallel with memory (26). An automatic test pattern generator transmits test patterns to memory input logic (33) to test its functionality. During testing operations, a memory array (26) is tri-stated. Tri-stating is accomplished by programming the automatic test pattern generator with a model of a tri-stating circuit (38) rather than actual memory array (26). Memory output logic (34) is tested by forcing its inputs through forcing circuitry (36). Forcing circuitry (36) forces the inputs to memory output logic (34) either by receiving a pattern from the automatic test pattern generator or by generating signals based on the outputs from memory input logic (33).
Bibliography:Application Number: US19950544740