Method of making ESD protection device structure for low supply voltage applications

A method for forming an ESD protection device, with reduced junction breakdown voltages, while simultaneously forming an integrated circuit, containing FET devices, has been developed. This invention features forming a large area, ESD protection diode, by using a first ion implantation step, of a sp...

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Bibliographic Details
Main Authors CHANG; KUN-ZEN, LIN; CHING-YUAN
Format Patent
LanguageEnglish
Published 07.10.1997
Edition6
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A method for forming an ESD protection device, with reduced junction breakdown voltages, while simultaneously forming an integrated circuit, containing FET devices, has been developed. This invention features forming a large area, ESD protection diode, by using a first ion implantation step, of a specific conductivity type, also used for the heavily doped source and drain regions of attached FET devices. After photoresist processing, used to mask the attached FET devices, a second ion implantation step, opposite in conductivity type then the first implant, is used to complete the ESD protection diode, for the ESD protection device. This large area diode reduces junction breakdown voltage, while allowing ESD current to be discharged more efficiently then for smaller ESD protection counterparts.
Bibliography:Application Number: US19960641768