Capacitor over bitline DRAM cell

• Main Authors: TENG; CLARENCE W, LIU; JIANN
• Format: Patent
• Language: English
• Published: 23.09.1997
• Edition: 6
• Subjects: ELECTRICITY

A DRAM array (100) having reduced bitline capacitance. The DRAM cell includes a pass transistor and a storage capacitor (150). An isolation structure (108) surrounds the DRAM cell. The bitline (140) is connected to a source/drain region (120b) of the pass transistor using a first polysilicon plug (1...