Page mode access memory controller including plural address latches and a comparator

• Main Author: KUSUDA; MASAHIRO
• Format: Patent
• Language: English
• Published: 01.07.1997
• Edition: 6
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; INFORMATION STORAGE; PHYSICS; STATIC STORES

A memory controller for a computer system having a processor and dynamic random access memories (DRAMs) which are grouped into banks, and having multiple latches associated respectively with the groups of DRAMs. Each latch stores a row address from the processor in response to a row address strobe (RAS) signal when the corresponding memory bank is selected and one of the latches is selected corresponding to the selected memory bank. The row address stored in the selected latch is compared by a comparator with a row address from the processor. Initially, a controller accesses the DRAMs of a bank currently selected using a first row address from the processor. If the same row of the selected bank is addressed again, a coincidence is detected by the comparator, and in response, the controller accesses the DRAMs using the same row address and a column address from the processor. If a noncoincidence is detected by the comparator, the controller accesses the DRAMs of the currently selected bank using a second row address and a column address from the processor.