State machine bus controller

A state machine bus controller for interfacing the CPU of a micro-computer based system with memory and I/O device is described. The controller, while capable of interfacing with a bus which is synchronous in nature, can maintain synchronous handshake with more than one type of microprocessor while...

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Bibliographic Details
Main Authors DUPONT; JEAN-PIERRE, SMOOT, III; CHARLES H, HERRING; JEFFRY V, LARSON; RONALD J, MATYSIAK; RICHARD
Format Patent
LanguageEnglish
Published 17.06.1997
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A state machine bus controller for interfacing the CPU of a micro-computer based system with memory and I/O device is described. The controller, while capable of interfacing with a bus which is synchronous in nature, can maintain synchronous handshake with more than one type of microprocessor while providing function and timing parameters to satisfy requirements of an asynchronous bus and more than one type of device which reside on the bus.
Bibliography:Application Number: US19950468030