Semiconductor memory device

• Main Authors: IMAMIYA; KENITI, MIYAMOTO; JUNICHI, IWATA; YOSHIHISA, NAKAMURA; HIROSHI
• Format: Patent
• Language: English
• Published: 11.03.1997
• Edition: 6
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

A semiconductor memory device according to the invention comprises a semiconductor substrate, a memory cell array having memory cells, each of which stores data, formed in matrix on the semiconductor substrate, a plurality of data latch circuits, each of which is arranged a one end of at least one bit line connected to the memory cell array and for latching programming data, control section for judging whether all of a plurality of latched data included in data latch groups constituted by the plurality of data latch circuits are the same as a first data or not and for controlling to change a potential of a plurality of first nodes according to the judging result, where there is one first node corresponding to each data latch circuit group, section for detecting potentials of the plurality of the first nodes corresponding to the plurality of data latch circuit groups, judging whether all data latched by the latch circuits includes in the plurality of latch circuit groups are the same as the first data and for controlling to change a potential of a plurality of second nodes according to the judging result, and section for detecting the potential of the plurality of second nodes and for outputting a judging result whether all of data latched by data latch circuits, which are included in the plurality of the data latch circuit groups, are the same as the first data or not.