Block architected static RAM configurable for different word widths and associated method for forming a physical layout of the static RAM

A method for building a compilable static RAM (SRAM). A central block structure (54) is formed which includes clock buffers (28), a delayed clock buffer (29), row address buffers (27), row deselect circuits (21), row driver circuits (22), output level translators, and a databus interface. A memory b...

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Bibliographic Details
Main Authors GRULA; JEROME A, SPENCE; NICHOLAS J, HOSHIZAKI; GARY W
Format Patent
LanguageEnglish
Published 05.11.1996
Edition6
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A method for building a compilable static RAM (SRAM). A central block structure (54) is formed which includes clock buffers (28), a delayed clock buffer (29), row address buffers (27), row deselect circuits (21), row driver circuits (22), output level translators, and a databus interface. A memory block macro (35) is built which includes a block of memory, precharge circuits, multiplexers, read/write multiplexers, and sense amplifiers. If multiple memory blocks are used a block deselect circuit (39) and row/block decoders (38) must be added to the memory block macro (35). A row and block deselection process is used in the SRAM architecture to simplify compilability and enhance speed.
Bibliography:Application Number: US19950489661