Reduced mask DRAM process

A process for fabricating stacked capacitor DRAM devices has been developed in which self aligned storage node contact structures, as well as bit line contact structures, are featured. A split polysilicon process has also been used to allow maskless source and drain ion implantation processing to be...

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Bibliographic Details
Main Author SUNG; JANMYE
Format Patent
LanguageEnglish
Published 27.08.1996
Edition6
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A process for fabricating stacked capacitor DRAM devices has been developed in which self aligned storage node contact structures, as well as bit line contact structures, are featured. A split polysilicon process has also been used to allow maskless source and drain ion implantation processing to be realized, thus reducing the number of photolithographic steps. A dual dielectric, interlevel insulator, is used to eliminate leakage between metal levels.
Bibliography:Application Number: US19950496015