Digital computer system having an improved direct-mapped cache controller (with flag modification) for a CPU with address pipelining and method therefor

A digital computer system having a "smart" cache controller that permits the system to take advantage of CPU address pipelining while minimizing the performance impact of a pipelined cache read miss in a system with a relatively low hit ratio such as a direct mapped cache.

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Bibliographic Details
Main Author CASSETTI; DAVID K
Format Patent
LanguageEnglish
Published 09.07.1996
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A digital computer system having a "smart" cache controller that permits the system to take advantage of CPU address pipelining while minimizing the performance impact of a pipelined cache read miss in a system with a relatively low hit ratio such as a direct mapped cache.
Bibliography:Application Number: US19940298989