Single event upset immune register with fast write access

• Main Authors: BIALAS, JR.; JOHN S, HOFFMAN; JOSEPH A
• Format: Patent
• Language: English
• Published: 11.06.1996
• Edition: 6
• Subjects: BASIC ELECTRONIC CIRCUITRY; ELECTRICITY; INFORMATION STORAGE; PHYSICS; PULSE TECHNIQUE; STATIC STORES

A single event upset hardened bi-stable CMOS circuit has a pair of cross coupled invertors with an isolation resistor in the path coupling the drains of the transistors in each invertor. Each invertor includes a PFET and a NFET pair coupled source to drain. An isolation resistor couples together the...