Single event upset immune register with fast write access

A single event upset hardened bi-stable CMOS circuit has a pair of cross coupled invertors with an isolation resistor in the path coupling the drains of the transistors in each invertor. Each invertor includes a PFET and a NFET pair coupled source to drain. An isolation resistor couples together the...

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Bibliographic Details
Main Authors BIALAS, JR.; JOHN S, HOFFMAN; JOSEPH A
Format Patent
LanguageEnglish
Published 11.06.1996
Edition6
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
INFORMATION STORAGE
PHYSICS
PULSE TECHNIQUE
STATIC STORES
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Summary:A single event upset hardened bi-stable CMOS circuit has a pair of cross coupled invertors with an isolation resistor in the path coupling the drains of the transistors in each invertor. Each invertor includes a PFET and a NFET pair coupled source to drain. An isolation resistor couples together the drains of each PFET-NFET pair and two low impedance conductive paths provide a direct coupling between the drains of each transistor of one invertor to common gate node of the other invertor.
Bibliography:Application Number: US19950391798