Coprocessor executing pipeline control for executing protocols and instructions

The interface portion of a coprocessor is provided with a FIFO (First-In First-Out) buffer and means for accepting instructions in succession. Pipeline control of the instructions becomes possible in this way, and protocol means associated with a microprocessor is also provided.

Saved in:
Bibliographic Details
Main Authors MORINAGA; SHIGEKI, NAKAGAWA; NORIO, KAZIWARA; HISASHI, ASAI; TAKESHI, TATEZAKI; JUNICHI, KIDA; HIROYUKI, OHBA; MAMORU, WATABE; MITSURU
Format Patent
LanguageEnglish
Published 02.04.1996
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:The interface portion of a coprocessor is provided with a FIFO (First-In First-Out) buffer and means for accepting instructions in succession. Pipeline control of the instructions becomes possible in this way, and protocol means associated with a microprocessor is also provided.
Bibliography:Application Number: US19920830460