Optical scan and alignment of devices under test

Apparatus for scanning an integrated circuit chip or other device under test (DUT) for defects and for visual alignment of chip electrical leads with leads of an electrical tester for testing the chip circuit(s). The apparatus provides an image forming system to provide a visually perceptible image...

Full description

Saved in:
Bibliographic Details
Main Author FRYE, JR.; RONALD E
Format Patent
LanguageEnglish
Published 02.01.1996
Edition6
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
SEMICONDUCTOR DEVICES
TESTING
Online AccessGet full text

Cover

More Information
Summary:Apparatus for scanning an integrated circuit chip or other device under test (DUT) for defects and for visual alignment of chip electrical leads with leads of an electrical tester for testing the chip circuit(s). The apparatus provides an image forming system to provide a visually perceptible image of the chip for chip scanning and chip lead alignment. The apparatus also provides means to translate the chip in a plane containing the chip and rotate the chip about an axis perpendicular to that plane to facilitate alignment of the chip leads with the corresponding electrical tester leads. A computer or operator views the chip through the image forming system and controls chip translation and rotation for scanning and lead alignment for subsequent chip testing.
Bibliography:Application Number: US19930079180