Data error correcting/detecting system and apparatus compatible with different data bit memory packages

Memory expansion using memory packages of different generations is performed without unnecessarily increasing the minimum memory capacity of a memory device and while obtaining a high error detecting ability and high reliability. In expanding the capacity of a memory device by using first generation...

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Bibliographic Details
Main Authors IWASAKI; KAZUYA, KOSUGE; HIROSHI, KIRIU; YOSHIO, KURIHARA; RYOICHI
Format Patent
LanguageEnglish
Published 12.09.1995
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Memory expansion using memory packages of different generations is performed without unnecessarily increasing the minimum memory capacity of a memory device and while obtaining a high error detecting ability and high reliability. In expanding the capacity of a memory device by using first generation 1Mx1 bit IC memory packages, second generation 4Mx4 bits IC memory packages, or third generation 16Mx8 bits IC memory packages, the total code length is set to 40 bits, a 4's multiple, within a range longer than the total code length necessary for S4ED and shorter than the total code length necessary for S8ED, and a reduced code is used for enhancing the S8ED function. In this manner, wasteful first generation IC memory packages can be reduced in number, and the error detecting ability of a memory device using third generation memory packages can be retained substantially the same as that of a memory device using first generation memory packages.
Bibliography:Application Number: US19920852954