Yield surface modeling methodology

A method for predicting yields for integrated circuit designs for given specification limits and process variations with respect to transistor parametric variations is based on a stastical analysis starting with response surface modeling techniques that relate desired circuit outcomes as a function...

Full description

Saved in:
Bibliographic Details
Main Authors FELDBAUMER; DAVID W, MAASS; ERIC
Format Patent
LanguageEnglish
Published 01.08.1995
Edition6
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
DATA PROCESSING SYSTEMS OR METHODS, SPECIALLY ADAPTED FORADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORYOR FORECASTING PURPOSES
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE,COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTINGPURPOSES, NOT OTHERWISE PROVIDED FOR
Online AccessGet full text

Cover

More Information
Summary:A method for predicting yields for integrated circuit designs for given specification limits and process variations with respect to transistor parametric variations is based on a stastical analysis starting with response surface modeling techniques that relate desired circuit outcomes as a function of a set of defined independent variables. The response surfaces are converted to discrete Cpk surfaces for all combinations of the independent variables. The Cpk surfaces are next converted to discrete percent yield surfaces for each of the circuit outcomes which then are combined to provide a composite yield surface comprising all desired parametric operating points of the outcomes that may be used to predict the circuit yield.
Bibliography:Application Number: US19950392664