Phase demodulation method and apparatus using asynchronous sampling pulses

• Main Author: PAFF; THOMAS M
• Format: Patent
• Language: English
• Published: 13.06.1995
• Edition: 6
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

A method is presented for efficient VLSI implementation of a narrowband BPSK or QPSK demodulator which minimizes filter processing requirements. The demodulator implements a digital filter which spans a time duration of 8 symbols to realize a square root of raised cosine filter. The disadvantage of a conventional FIR filter, is that it requires a fixed ratio between the input sample rate and the FIR filter output rate. The subject invention employs a unique, flexible digital filter which provides one output per symbol while the input sample rate may vary from a low rate approaching two samples per symbol to over 128 samples per symbol. A key element of this approach is the digital phase locked loop used for symbol tracking which employs a direct digital synthesizer (DDS) as the frequency control element. In addition to providing symbol timing to the accuracy of the sample clock, the DDS also provides a fine measure of symbol timing phase at each sample clock. This high resolution timing phase information provided by the symbol timing NCO is used to select the filter coefficients to be applied at each sample. The resulting implementation is practical for a sample rate approaching 2 samples-per-symbol and can be used with sample rates as high as several hundred samples-per-symbol. The low clock rate permits very low power consumption for a fixed carrier frequency and symbol rate application, or a high clock rate can be used to enable the demodulator to be tuned over a wide range of potential carrier frequencies and symbol rates.