Data transfer apparatus

A parallel processing system enabling a mixed transfer of packets of different lengths is achieved. The data transfer apparatus in this parallel processing system comprises four address controllers. During the first data transfer the third address controller is used for sending and the first address...

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Bibliographic Details
Main Author OKABAYASHI; ICHIRO
Format Patent
LanguageEnglish
Published 18.04.1995
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A parallel processing system enabling a mixed transfer of packets of different lengths is achieved. The data transfer apparatus in this parallel processing system comprises four address controllers. During the first data transfer the third address controller is used for sending and the first address controller is used for receiving data. During the second transfer, the fourth address controller is used for sending, and the second address controller is used for receiving. When the first and second transfer operations are mixed, the first and second address controllers are selectively used during receiving, and the third and fourth address controllers are selectively used during sending. Each of the address controllers changes the address only after packet transfer is completed. The header of the packet contains a packet length field, which is interpreted to enable simultaneous, dynamic handling of plural packets of different lengths. As a result, packets can be transferred without deadlocks occurring even when packets of different lengths are mixed.
Bibliography:Application Number: US19920995873