Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills

• Main Authors: WADE; NICHOLAS D, STAMM; REBECCA L
• Format: Patent
• Language: English
• Published: 04.04.1995
• Edition: 6
• Subjects: BLASTING; CALCULATING; COMBUSTION ENGINES; COMBUSTION ENGINES IN GENERAL; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; HEATING; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS; INTERNAL-COMBUSTION PISTON ENGINES; LIGHTING; MECHANICAL ENGINEERING; PHYSICS; WEAPONS

A processor and method for preventing access to a locked memory block in a multiprocessor computer system. The processor has a cache memory and records a memory lock in a content-addressable memory separate from the cache memory. Preferably, outstanding cache fills are recorded in the same content addressable memory as memory locks, and a memory lock or an outstanding cache fill delays the execution of a cache coherency request upon the same memory block. When a cache coherency request is received from another processor, the address of the cache coherency request is compared to addresses stored in the content addressable memory, and when there is a match, a bit in the matching entry is set to indicate a delayed request that is executed after the lock is unlocked or the cache is refilled. In a specific embodiment, a memory lock or an outstanding cache fill also stalls a processor read or write to the same memory block.