Circuit for providing a high-speed logic transition

An ECL gate (32) includes a speedup circuit (34) comprising an NPN transistor (36) having its base connected to the IN signal to the gate (32). The PNP transistor drives an NPN transistor (40) to provide faster output transitions responsive to low-to-high transition to the IN signal.

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Bibliographic Details
Main Author OVENS; KEVIN M
Format Patent
LanguageEnglish
Published 16.08.1994
Edition5
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Summary:An ECL gate (32) includes a speedup circuit (34) comprising an NPN transistor (36) having its base connected to the IN signal to the gate (32). The PNP transistor drives an NPN transistor (40) to provide faster output transitions responsive to low-to-high transition to the IN signal.
Bibliography:Application Number: US19920985734