Plural-bit recoding multiplier

A recoding method of two or more bit groups to reduce the number of partial products and their hardware implementation. Unique complementing scheme, pre-addition of complementing carriers and derivation of sign extensions also reduce hardware implementation as well as allowing the multiplier to hand...

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Bibliographic Details
Main Authors MALINOWSKI; CHRISTOPHER W, YOUNG; WILLIAM R
Format Patent
LanguageEnglish
Published 16.11.1993
Edition5
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A recoding method of two or more bit groups to reduce the number of partial products and their hardware implementation. Unique complementing scheme, pre-addition of complementing carriers and derivation of sign extensions also reduce hardware implementation as well as allowing the multiplier to handle any combination of input and output formats The principles are also applied to multiplier/accumulators and complex multipliers.
Bibliography:Application Number: US19920973932