Chip edge interconnect overlay element

• Main Authors: IMKEN; RONALD L, FRANKENY; RICHARD F
• Format: Patent
• Language: English
• Published: 20.07.1993
• Subjects: BASIC ELECTRIC ELEMENTS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS; PRINTED CIRCUITS; SEMICONDUCTOR DEVICES

A chip overlay element is formed of a flexible substrate of polymer having electrically conductive material applied to one side thereof and circuitized to form signal lines. A metal stiffener/heat spreader is laminated to the polymer on the opposite side of the conductor. I/Os are formed on one end of the signal lines of the circuitized layer (near the end of the overlay element) and interconnection pads, bumps, or the like are formed on the opposite end (near the center of the element). The metal stiffener is then etched to form three distinct areas. The chip edge is then placed on the center metal stiffener area and bonded, with the other two stiffener areas being bent around the chip and bonded to the corresponding chip sides. The original I/Os are then electrically connected to the I/Os formed on the signal lines of the overlay element.