Modular self-test for embedded SRAMS

A self-test that is variable to test an SRAM that is embedded on a semiconductor die is achieved. The self-test is performed by a modular self-test circuitry that can be varied to permit generating addresses, and data patterns for various SRAM architectures and sizes. An address block develops addre...

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Bibliographic Details
Main Authors GRULA; JEROME A, SPENCE; NICHOLAS J, HOSHIZAKI; GARY W
Format Patent
LanguageEnglish
Published 22.06.1993
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
TESTING
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Summary:A self-test that is variable to test an SRAM that is embedded on a semiconductor die is achieved. The self-test is performed by a modular self-test circuitry that can be varied to permit generating addresses, and data patterns for various SRAM architectures and sizes. An address block develops addresses which define a test location or test word within the SRAM. The address block also develops a time delay which is used during a data retention test. A data block develops test patterns that are written into SRAM test locations. The data block also analyzes data read from SRAM test locations or test words. Both the address block and the data block are formed by combining a number of individual address or data cells, thereby providing addresses and data patterns for a variety of different SRAM configurations. A control block operates the address block, the data block, and the SRAM to perform two memory tests. A fault analysis test identifies faults within and between memory locations, and a data retention test identifies memory retention errors.
Bibliography:Application Number: US19900633862