Method of producing a bipolar transistor with a laterally graded emitter (LGE) employing a refill method of polycrystalline silicon

• Main Authors: KIM; MOON-HO, HAN; SEOG-HEON, WON; TAE-YOUNG, KO; JANG-MAN
• Format: Patent
• Language: English
• Published: 15.09.1992
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; SEMICONDUCTOR DEVICES; TECHNICAL SUBJECTS COVERED BY FORMER USPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS

A method for manufacturing a bipolar transistor semiconductor device for preventing a degradation phenomenon of the transistor resulting from a reduction of a lateral electric field intensity. This is achieved by grading an emitter junction by way of refilling an emitter window with polycrystalline silicon. The resulting transistor structure overcomes the etch stop barrier by removing layer of oxide disposed below a layer of nitride along the region where formation of removing sidewalls of polycrystalline silicon have been formed. Subsequently, a doping distribution of the laterally graded emitter junction can easily be obtained by refilling the emitter window with the removed oxide layer with polycrystalline silicon. Because the shallowness of the oxide layer can be selectively and easily controlled, a thickness of the sidewalls is chosen which most efficiently raises the lateral electric field intensity of the transistor junction.