Adaptive associative memory comprising synapes of CMOS transistors

An associative memory for storing an n-bit stored vector in m different states comprises n first amplifiers connected between n input terminals and n output terminals, and m second amplifiers to feedback to the input side the designated states of the stored vectors. Synapses of the storing unit stor...

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Bibliographic Details
Main Author JEONG; HO-SUN
Format Patent
LanguageEnglish
Published 23.07.1991
Subjects
CALCULATING
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
COMPUTING
COUNTING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:An associative memory for storing an n-bit stored vector in m different states comprises n first amplifiers connected between n input terminals and n output terminals, and m second amplifiers to feedback to the input side the designated states of the stored vectors. Synapses of the storing unit store the above mentioned stored vectors in the a binary 1 or 0; synapses of the label units couple the respective intersections between the input and output lines of the second amplifiers; and synapses of the vector units couple the intersections between the output lines of the first amplifiers and the input lines of the second amplifiers. According to the present invention, the outputs of the amplifiers are stabilized, so that stabilized operations can be obtained.
Bibliography:Application Number: US19900473465