Nonvolatile semiconductor memory having a stress test circuit

• Main Authors: OHTSUKA; NOBUAKI, MIYAMOTO; JUNICHI, ATSUMI; SHIGERU
• Format: Patent
• Language: English
• Published: 12.03.1991
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

In a nonvolatile semiconductor memory, a plurality of nonvolatile semiconductor memory cells (M11 - Mmn) are arranged in a matrix form. Each of the memory cells (M11 - Mmn) is connected to corresponding one of bit lines (BL1 - BLm) and corresponding one of word lines (WL1 - WLn). The one ends of the bit lines (BL1 - BLm) are commonly connected to a programming transistor (7) for setting a programming mode through transistors (1, 2, 3, 4) for selecting the bit lines. The transistors (3, 4) are connected to column decoders (5-1, 5-2) and word lines are connected to a row decoder (6). Furthermore, the other ends of the bit lines (M11 - Mmn) are connected to a common connecting line (17) through transistors (10) for setting a test mode and the common correctly line (12) is connected to a mode (C) between transistor (12) and a series circuit (13) of transistor (12) and a dummy memory cell (15) in a clamp circuit (11). The transistor (12) of the clamp circuit (11) is connected to a high voltage and the series circuit (13) is connected to the ground. In the test mode, the programming transistor (7) and the bit line selecting transistors (1, 2, 3, 4) are turn off and the test mode transistors (10) and the transistor (12, 14) connected of the clamp circuit (11) are turn on. Thus, a test voltage is applied to the memory cells (M11 - Mmn) through the common connecting line (17), the test mode transistors (10) and the bit lines (BL1 - BLm).