Architecture for a flash erase EEPROM memory

An EEPROM device provides increased speed and less susceptibility to soft writes during reading and programming operations. A circuit design and operating method obviates the need for applying a high programming or erase voltage in the path between the memory array and sense amplifier. Such high pro...

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Bibliographic Details
Main Author AMIN; ALAAELDIN
Format Patent
LanguageEnglish
Published 12.03.1991
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:An EEPROM device provides increased speed and less susceptibility to soft writes during reading and programming operations. A circuit design and operating method obviates the need for applying a high programming or erase voltage in the path between the memory array and sense amplifier. Such high programming and erase voltages are applied, as needed, directly to the memory array, thereby allowing all transistors which carry signals from the memory array to the sense amplifier to be fabricated as low voltage devices, thereby increasing their speed of operation and thus the speed of operation of the memory device as a whole. By applying the relatively high programming and erase voltages to the source of the memory transistors, and reading from the drain of the memory transistors, the source and drain as well as associated circuitry are fabricated to optimize their intended functions.
Bibliography:Application Number: US19880275380