Data processing system employing two address translators, allowing rapid access to main storage by input/output units

• Main Authors: SHINOZAKI; MASATSUGU, SADAMITSU; HITOSHI, KONDO; MEGUMU, FUKUOKA; KAZUHIKO, KAMIYA; SHUJI
• Format: Patent
• Language: English
• Published: 25.09.1990
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

In a data processing system having a central processing unit, at least an input/output unit such as an MT unit or a floppy disk unit, a memory, an address bus, a first address translation unit, a second address translation unit, and an address selection unit, an output address from the central processing unit is translated by the first address translation unit to supply a resultant address to the address bus and, an output address from the input/output unit is directly fed to the address bus. An address on the address bus is delivered to the address selection unit, and the address selection unit selectively supplies the memory with the output address delivered from the first translation unit onto the address bus or with the resultant address obtained by translating the output address from the input/output unit by means of the second translation unit. In this configuration, the second address translation unit, to translate an address from the input/output unit, is disposed at an input to the memory, which eliminates the necessity for a translator on the side of the input/output device.