Fabrication method for high speed and high packing density semiconductor device (BiCMOS)

A fabrication method for a high speed and high packing density semiconductor device (BiCMOS) in which high speed polysilicon self-aligned bipolar transistors and high packing density CMOS are contained on the same wafer in such a manner that simplicity in fabrication is attained, while the high spee...

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Bibliographic Details
Main Authors LEE; JIN H, CHAI; SANG HUN, KIM; YEO H, KIM; KWANG S, KOO; YOUNG S
Format Patent
LanguageEnglish
Published 04.09.1990
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS
SEMICONDUCTOR DEVICES
TECHNICAL SUBJECTS COVERED BY FORMER USPC
TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS
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Summary:A fabrication method for a high speed and high packing density semiconductor device (BiCMOS) in which high speed polysilicon self-aligned bipolar transistors and high packing density CMOS are contained on the same wafer in such a manner that simplicity in fabrication is attained, while the high speed of operation and the high packing density of array are simultaneously realized.
Bibliography:Application Number: US19880224020