Triple-poly 4T static ram cell with two independent transistor gates

A 4T static RAM cell (10) comprising a flip-flop with two pull-down transistors (18, 20) and two pass-gate transistors (12, 14) is fabaricated employing two separate gate oxide formations (74, 76) and associated separate polysilicon depositions (52a -b, 56). Two reduced area contacts (58, 60) connec...

Full description

Saved in:
Bibliographic Details
Main Authors KLEIN; RICHARD K, SANDER; CRAIG S, CHOI; TAT C
Format Patent
LanguageEnglish
Published 21.08.1990
Edition5
Subjects
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:A 4T static RAM cell (10) comprising a flip-flop with two pull-down transistors (18, 20) and two pass-gate transistors (12, 14) is fabaricated employing two separate gate oxide formations (74, 76) and associated separate polysilicon depositions (52a -b, 56). Two reduced area contacts (58, 60) connect to the nodes (26, 30) of the circuit (10). The reduced area butting contacts comprise vertically-disposed, doped polysilicon plugs (94), which intersect and electrically interconnect buried polysilicon layers (load poly 88, gate poly 52a) with doped silicon regions (80) in a bottom layer. Adding the processing steps of forming separate gate oxides for the pull-down and pass-gate transistors results in a smaller cell area and reduces the requirements of the contacts from three to two. Further, the separate gate oxidations permit independent optimization of the pull-down and pass-gate transistors.
Bibliography:Application Number: US19880280782