Virtual bit map processor

• Main Author: BLANK; WILLIAM T
• Format: Patent
• Language: English
• Published: 03.07.1990
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

A single instruction multiple data parallel processor has a rectangular array of processing elements which is smaller than the array of data to be processed. The array of data to be processed is divided into a number of segments, each equal in size to the processing element array. Each processing element includes a memory for storing one or more data values corresponding to one data element in each of these segments of the data array. To execute an instruction on all the data, the processing elements execute the instruction on one segment of the data array at a time, repeating the process until all the data has been processed. To do this, a primary address controller generates a sequence of segment address values for each instruction to be executed. The processing elements along the periphery of the processing element array are called edge processing elements. An edge address controller generates edge address values corresponding to the segment addresses of the segments neighboring the segment currently being addressed by the primary address controller. Each processing element is coupled to its neighbors so that it can execute instructions which require access to neighboring data elements. To enable edge processing elements to access neighboring data elements, each edge processing element has special hardware for accessing data values stored in a memory location corresponding to one of the edge address values.