Memory with cache register interface structure
A memory having at least a pair of cache registers between the data input and output ports and the read and write ports of a memory matrix and controls to alternate the interconnection between the cache registers and the data input/output ports and the read/write terminals of the memory matrix, such...
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| Main Author | |
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| Format | Patent |
| Language | English |
| Published |
19.12.1989
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| Subjects | |
| Online Access | Get full text |
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| Abstract | A memory having at least a pair of cache registers between the data input and output ports and the read and write ports of a memory matrix and controls to alternate the interconnection between the cache registers and the data input/output ports and the read/write terminals of the memory matrix, such that while one cache register is connected to the data input/output port, the other cache register is connected to a port of the memory. Look-ahead logic is provided to generate the next address of the memory location which is to be written into or read from with simultaneous transfer of information to or from the cache register which is connected to the memory ports. |
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| AbstractList | A memory having at least a pair of cache registers between the data input and output ports and the read and write ports of a memory matrix and controls to alternate the interconnection between the cache registers and the data input/output ports and the read/write terminals of the memory matrix, such that while one cache register is connected to the data input/output port, the other cache register is connected to a port of the memory. Look-ahead logic is provided to generate the next address of the memory location which is to be written into or read from with simultaneous transfer of information to or from the cache register which is connected to the memory ports. |
| Author | MALINOWSKI; CHRISTOPHER W |
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| Notes | Application Number: US19880289748 |
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| PublicationDateYYYYMMDD | 1989-12-19 |
| PublicationDate_xml | – month: 12 year: 1989 text: 19891219 day: 19 |
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| PublicationYear | 1989 |
| RelatedCompanies | HARRIS CORPORATION |
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| Snippet | A memory having at least a pair of cache registers between the data input and output ports and the read and write ports of a memory matrix and controls to... |
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| SubjectTerms | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| Title | Memory with cache register interface structure |
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