Memory with cache register interface structure

A memory having at least a pair of cache registers between the data input and output ports and the read and write ports of a memory matrix and controls to alternate the interconnection between the cache registers and the data input/output ports and the read/write terminals of the memory matrix, such...

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Bibliographic Details
Main Author MALINOWSKI; CHRISTOPHER W
Format Patent
LanguageEnglish
Published 19.12.1989
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A memory having at least a pair of cache registers between the data input and output ports and the read and write ports of a memory matrix and controls to alternate the interconnection between the cache registers and the data input/output ports and the read/write terminals of the memory matrix, such that while one cache register is connected to the data input/output port, the other cache register is connected to a port of the memory. Look-ahead logic is provided to generate the next address of the memory location which is to be written into or read from with simultaneous transfer of information to or from the cache register which is connected to the memory ports.
Bibliography:Application Number: US19880289748