Integrated-circuit power-up pulse generator circuit

A circuit for providing a "power-up" signal pulse in response to energization of an integrated circuit logic array by a power supply. The circuit is comprised of a pulse-generating circuit and of an optional pulse-delay means. The pulse-generating circuit means detects the presence or abse...

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Bibliographic Details
Main Author KADAKIA; SHAILESH R
Format Patent
LanguageEnglish
Published 19.12.1989
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
INFORMATION STORAGE
PHYSICS
PULSE TECHNIQUE
STATIC STORES
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Summary:A circuit for providing a "power-up" signal pulse in response to energization of an integrated circuit logic array by a power supply. The circuit is comprised of a pulse-generating circuit and of an optional pulse-delay means. The pulse-generating circuit means detects the presence or absence of change in energization voltage potential and, in response to energization, develops an output pulse using ratioed complementary-metal-oxide-semiconductor (CMOS) logic to detect energization status during the ramp increase of the supply voltage. A feedback circuit is used to detect completion of the ramp increase and to deactivate the circuit to minimize power required for steady-state operation. The optional pulse-delay means is illustrated as narrow-width, long-channel CMOS inverters with optional capacitor loading.
Bibliography:Application Number: US19880172532