Deterministic clock control apparatus for a data processing system

A clock control apparatus that stops a system clock in a high performance high speed computer a determined number of system clock cycles after the generation of the clock control signal by a digital computer. The apparatus receives a basic clock signal and the clock control signal and generates a sy...

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Bibliographic Details
Main Authors WANG; EUGENE T, CHIOU; JONGWEN, SI; STEPHEN S. C
Format Patent
LanguageEnglish
Published 30.05.1989
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A clock control apparatus that stops a system clock in a high performance high speed computer a determined number of system clock cycles after the generation of the clock control signal by a digital computer. The apparatus receives a basic clock signal and the clock control signal and generates a system clock for the system. The system clock includes a normal system clock signal and at least one early system clock signal. The basic clock is provided through a delay tap generating a normal basic clock signal and at least one early basic clock signal. In addition, a control state machine receiving the normal basic clock signal and the at least one early basic clock signal and responsive to the clock control signal is provided for starting and stopping the system clock. The clock control signal is synchronized with the earliest system clock and supplied to the clock control state machine.
Bibliography:Application Number: US19860896415