Layout for stable high speed semiconductor memory device

In a semiconductor memory device, a memory cell array is separated into at least two portions on a substrate, and a serial memory element, such as a shift register, and control signal lines are collectively disposed between the two memory cell array portions, and by this arrangement, the length of t...

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Bibliographic Details
Main Authors KAWAI; HIDEKI, FUJII; MASARU, OHTA; KIYOTO, MAEYAMA; YOSHIKAZU
Format Patent
LanguageEnglish
Published 03.01.1989
Edition4
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:In a semiconductor memory device, a memory cell array is separated into at least two portions on a substrate, and a serial memory element, such as a shift register, and control signal lines are collectively disposed between the two memory cell array portions, and by this arrangement, the length of the control signal lines and data lines can be minimized so that the stray or parasitic capacitance is reduced, and a higher speed and stable operation of the device is thereby realized.
Bibliography:Application Number: US19870015349