FET gate current limiter circuit

• Main Author: NOUFER; GLENN E
• Format: Patent
• Language: English
• Published: 13.09.1988
• Edition: 4
• Subjects: BASIC ELECTRONIC CIRCUITRY; ELECTRICITY; PULSE TECHNIQUE

A GaAs logic circuit including a current control FET that provides high current for switching an output FET, but limits the forward biasing of the output FET at the end of a transition to input logic 1 by controlling the steady state value of current to a gate of the output FET, which limits the voltage applied to the gate of the output FET to a given value. A bias circuit referenced to the voltage applied to the source of the output FET applies a nominal gate voltage to the current control FET. The value of the nominal gate voltage is such as is required to limit the value of the steady state current to the gate of the output FET to that which limits the voltage applied to such gate to the desired given value. Such nominal gate voltage is obtained by shifting the source voltage by the amount of the nominal threshold voltage VTe of an enhancement-mode FET of the bias circuit. If the nominal threshold voltage VTe varies from nominal in processing or due to operating temperature variations, the bias circuit shifts the gate voltage from nominal so that the actual voltage applied to the gate of the current control FET offsets the corresponding increase in the threshold voltage of the current control FET. As a result, the actual steady state current conducted by the GaAs logic circuit is relatively independent of such process and temperature variations.