Bipolar RAM cell
A memory cell is provided having reduced read and write times, and a large current differential between the standby mode and the read mode. A pair of cross-coupled NPN transistors have their emitters coupled to a lower word line and their collectors coupled to an upper word line by a first and secon...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
29.09.1987
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Edition | 4 |
Subjects | |
Online Access | Get full text |
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Abstract | A memory cell is provided having reduced read and write times, and a large current differential between the standby mode and the read mode. A pair of cross-coupled NPN transistors have their emitters coupled to a lower word line and their collectors coupled to an upper word line by a first and second load, respectively. First and second NPN sense transistors each have a base coupled to the base of one of the cross-coupled transistors, an emitter coupled to a first and a second bit line, respectively, and a collector coupled to receive a supply voltage. |
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AbstractList | A memory cell is provided having reduced read and write times, and a large current differential between the standby mode and the read mode. A pair of cross-coupled NPN transistors have their emitters coupled to a lower word line and their collectors coupled to an upper word line by a first and second load, respectively. First and second NPN sense transistors each have a base coupled to the base of one of the cross-coupled transistors, an emitter coupled to a first and a second bit line, respectively, and a collector coupled to receive a supply voltage. |
Author | STIPANUK; JAMES J BIRRITTELLA; MARK S |
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Notes | Application Number: US19850809551 |
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Snippet | A memory cell is provided having reduced read and write times, and a large current differential between the standby mode and the read mode. A pair of... |
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Title | Bipolar RAM cell |
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