Bipolar RAM cell

A memory cell is provided having reduced read and write times, and a large current differential between the standby mode and the read mode. A pair of cross-coupled NPN transistors have their emitters coupled to a lower word line and their collectors coupled to an upper word line by a first and secon...

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Bibliographic Details
Main Authors BIRRITTELLA; MARK S, STIPANUK; JAMES J
Format Patent
LanguageEnglish
Published 29.09.1987
Edition4
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory cell is provided having reduced read and write times, and a large current differential between the standby mode and the read mode. A pair of cross-coupled NPN transistors have their emitters coupled to a lower word line and their collectors coupled to an upper word line by a first and second load, respectively. First and second NPN sense transistors each have a base coupled to the base of one of the cross-coupled transistors, an emitter coupled to a first and a second bit line, respectively, and a collector coupled to receive a supply voltage.
Bibliography:Application Number: US19850809551