Validity checking arrangement for extended memory mapping of external devices

• Main Authors: CHAPMAN; HARRY A, JOHNSTON; JEFFREY J, LADEWSKI; CHESTER T
• Format: Patent
• Language: English
• Published: 23.07.1985
• Edition: 3
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; PHYSICS; SELECTING

In a telecommunications switching system, a CPU utilizes memory mapped access to a number of duplex external devices and other memories. A validity checking arrangement provides for detecting invalid external device unit numbers for memory mapped accesses by the CPU. In addition, this validity check...