Validity checking arrangement for extended memory mapping of external devices

In a telecommunications switching system, a CPU utilizes memory mapped access to a number of duplex external devices and other memories. A validity checking arrangement provides for detecting invalid external device unit numbers for memory mapped accesses by the CPU. In addition, this validity check...

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Bibliographic Details
Main Authors CHAPMAN; HARRY A, JOHNSTON; JEFFREY J, LADEWSKI; CHESTER T
Format Patent
LanguageEnglish
Published 23.07.1985
Edition3
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
SELECTING
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Summary:In a telecommunications switching system, a CPU utilizes memory mapped access to a number of duplex external devices and other memories. A validity checking arrangement provides for detecting invalid external device unit numbers for memory mapped accesses by the CPU. In addition, this validity checking arrangement will determine that the CPU's operating software has attempted a memory mapped access with an invalid unit number or that a true hardware fault exists.
Bibliography:Application Number: US19830506565