Method for manufacturing an electrical interconnection by selective tungsten deposition
A structure for an electrical interconnection suitable for a semiconductor integrated circuit is made by a process utilizing selective tungsten deposition at low pressure to form an intermediate conductive layer without significantly ablating nearby insulating material.
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Main Author | |
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Format | Patent |
Language | English |
Published |
14.05.1985
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Edition | 3 |
Subjects | |
Online Access | Get full text |
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Summary: | A structure for an electrical interconnection suitable for a semiconductor integrated circuit is made by a process utilizing selective tungsten deposition at low pressure to form an intermediate conductive layer without significantly ablating nearby insulating material. |
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Bibliography: | Application Number: US19830490381 |