Method of fabricating three-dimensional semiconductor devices utilizing CeO2 and ion-implantation

• Main Authors: TAKASU; SHINICHIRO, MIZUTANI; YOSHIHISA
• Format: Patent
• Language: English
• Published: 30.10.1984
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; SEMICONDUCTOR DEVICES; TECHNICAL SUBJECTS COVERED BY FORMER USPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS

A method for fabricating a three-dimensional multi-layer integrated circuit of single crystalline CeO2 and Si is proposed. This method is characterized in that a single crystalline CeO2 insulation layer, or the like, is formed on a single crystalline Si substrate. An isolation region is formed in the single crystalline Si substrate. The region is transformed into a SiO2 insulation layer by selectively introducing oxygen ions through the single crystalline CeO2 insulation layer and reacting the oxygen ions with the single crystalline Si. An epitaxial growth single crystalline Si layer is formed on the single crystalline CeO2 insulation layer. Predetermined processes, such as forming a single crystalline CeO2 layer, are performed thereafter to form the three-dimensional structures of semiconductor elements such as MOS transistors and bipolar transistors with high packing density and reliability.