Planar doped barrier gate field effect transistor

Disclosed is an epitaxial layer field effect transistor having a planar doped barrier gate formed on an n-type semiconductor planar channel region between drain and source terminals formed on the surface of the channel region. The semiconductor channel region is fabricated on a semiconductor substra...

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Bibliographic Details
Main Authors MALIK; ROGER J, AUCOIN; THOMAS R
Format Patent
LanguageEnglish
Published 10.04.1984
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Disclosed is an epitaxial layer field effect transistor having a planar doped barrier gate formed on an n-type semiconductor planar channel region between drain and source terminals formed on the surface of the channel region. The semiconductor channel region is fabricated on a semiconductor substrate, preferably GaAs and being separated therefrom by one or more semiconductor planar buffer regions. The planar doped barrier gate comprises an n+- pi -p+- pi structure grown by molecular beam epitaxy over the n-type channel region. Application of an electrical potential to the gate modulates the channel charge depletion in the semiconductor channel region underlying the gate causing a variation in the channel conductance laterally between the source and drain terminals.
Bibliography:Application Number: US19810323858