Programmable mode select by reset

A mode selection circuit is disclosed which is suitable for configuring a data processor at the time at which the data processor is initialized with a reset signal. Mode selection latches are coupled to terminals normally used as an input/output port for the data processor and the latches are clocke...

Full description

Saved in:
Bibliographic Details
Main Authors TIETJEN; DONALD L, SHAW; PERN, WILES; MICHAEL F
Format Patent
LanguageEnglish
Published 14.02.1984
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:A mode selection circuit is disclosed which is suitable for configuring a data processor at the time at which the data processor is initialized with a reset signal. Mode selection latches are coupled to terminals normally used as an input/output port for the data processor and the latches are clocked with a signal generated by a level detector circuit which senses the reset signal. The mode selection latches are programmed by applying appropriate logic levels to the terminals of the input/output port at the time at which the data processor is being reset. The circuitry is adapted for allowing the connection of a diode from a terminal of the input/output port to the reset terminal of the data processor in order to program a low logic level into the corresponding mode detection latch.
Bibliography:Application Number: US19800192157