Integrated semiconductor memory and method of operating same

An integrated semiconductor memory having memory cells which have (or are designed to have) inherent asymmetrical access times for the distinguishable memory states thereof. The memory is operated on the basis of the shorter access time. This is accomplished by utilizing an oppositely asymmetrical s...

Full description

Saved in:
Bibliographic Details
Main Authors NAJMANN; KNUT, HEIMEIER; HELMUT H, KLEIN; WILFRIED, WERNICKE; FRIEDRICH C
Format Patent
LanguageEnglish
Published 26.01.1982
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:An integrated semiconductor memory having memory cells which have (or are designed to have) inherent asymmetrical access times for the distinguishable memory states thereof. The memory is operated on the basis of the shorter access time. This is accomplished by utilizing an oppositely asymmetrical sense system, preferably in the form of a pre-set sense latch. For example, in the case of a digital memory with the reading of a "0" state having a shorter access time than the reading of a "1" state, at the beginning of a read operation a sense latch is set to the (slower) "1" state. Thus, only in the case of reading a "0" is the state of the latch changed to the "0" state. Thus, the actual access time is no longer determined by the longer access time, namely, the reading of a "1". The access time is determined by the shorter access time, namely, the reading of a "0". The concept may also be used if the sense latch has an asymmetric access time. Then it is advantageous to intentionally choose a corresponding asymetrical memory cell design.
Bibliography:Application Number: US19800133383