Refresh control system

In a refresh control system including a main memory having a volatile memory, at least one processing unit for accessing the main memory, a memory bus for effecting signal transfer between the main memory and the processing unit and a supervision circuit for allotting use of the memory bus in respon...

Full description

Saved in:
Bibliographic Details
Main Authors CHIBA; TSUNEYO, UMEZAWA; KIYOSHI, KADONO; SHINJI
Format Patent
LanguageEnglish
Published 19.06.1979
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:In a refresh control system including a main memory having a volatile memory, at least one processing unit for accessing the main memory, a memory bus for effecting signal transfer between the main memory and the processing unit and a supervision circuit for allotting use of the memory bus in response to a request signal, the refresh control system is characterized by a refresh control circuit for transferring the request signal to the supervision circuit at the time the refresh signal is required and for commanding the initiation of the refresh operation to the main memory in response to a grant signal from the supervision circuit.
Bibliography:Application Number: US19760737350