SEMICONDUCTOR MEMORY DEVICE

Active regions defined by device isolation layer are provided on a substrate. A word line crossing the active regions and a gate dielectric layer between the word line and the active regions are provided. A capping insulating pattern covering an upper surface of the word line and a bit line on the w...

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Bibliographic Details
Main Authors CHOI, Hyun Seung, LEE, Jun-Bum, KWON, Jihye, KIM, Junsoo, CHOI, Jae Hyun, KONG, Dongsik
Format Patent
LanguageEnglish
Published 10.10.2024
Subjects
ELECTRICITY
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Summary:Active regions defined by device isolation layer are provided on a substrate. A word line crossing the active regions and a gate dielectric layer between the word line and the active regions are provided. A capping insulating pattern covering an upper surface of the word line and a bit line on the word line are provided. The word line may include a first conductive pattern and a second conductive pattern on the first conductive pattern. The first conductive pattern may include a first metal element. The second conductive pattern may include the first metal element, a work function adjustment element, and a diffusion barrier element. An atomic radius of the diffusion barrier element may be smaller than an atomic radius of the first metal element.
Bibliography:Application Number: US202318493196