ADDRESS TRANSLATION IN A MULTI-NODE COMPUTING SYSTEM
A system and method for address translation in a multi-node computing system. In some embodiments, the system includes a first node. The first node may include: a core; and a global address translation circuit, the core including: a core processing circuit; and a memory management unit configured to...
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Main Authors | , , , , , |
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Format | Patent |
Language | English |
Published |
03.10.2024
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Subjects | |
Online Access | Get full text |
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Summary: | A system and method for address translation in a multi-node computing system. In some embodiments, the system includes a first node. The first node may include: a core; and a global address translation circuit, the core including: a core processing circuit; and a memory management unit configured to map local virtual addresses to global virtual addresses, the global address translation circuit being configured to map global virtual addresses to global physical addresses. |
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Bibliography: | Application Number: US202318534532 |