STATIC RANDOM-ACCESS MEMORY AND INTEGRATED CIRCUIT LAYOUT THEREOF

The present application discloses a static random-access memory. Upon an entry to a sleep mode, a power switch transistor in a word line drive power supply module is off, thus controlling the elimination of a leakage path of a word line driver, so that leakage power consumption of the SRAM is mainta...

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Bibliographic Details
Main Authors KUROKI, Koichi, CAO, Mu
Format Patent
LanguageEnglish
Published 26.09.2024
Subjects
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:The present application discloses a static random-access memory. Upon an entry to a sleep mode, a power switch transistor in a word line drive power supply module is off, thus controlling the elimination of a leakage path of a word line driver, so that leakage power consumption of the SRAM is maintained at that of an on standby state of a normal operating mode or a data retention mode. The entry to and exit from the sleep mode of the SRAM can be carried out flexibly and quickly, without complying with strict timing requirements required by stepwise powering-on and stepwise powering-off, thereby facilitating the implementation of a leakage control function without increasing a layout size. The present application discloses an integrated circuit layout of the static random-access memory.
Bibliography:Application Number: US202418582183