TRACING CIRCUIT INCLUDING MEMORY MAPPED TRACE BUFFERS IN NODES OF A MESH NETWORK

Tracing circuits are disposed within each node circuit in a mesh network to debug problems found during development. The tracing circuit disclosed includes a trace read interface for accessing trace packets stored in a trace buffer at entries that are mapped to system memory addresses. Processing ci...

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Bibliographic Details
Main Authors Kirtane, Gaurav Sanjeev, Chamarty, Vinod
Format Patent
LanguageEnglish
Published 26.09.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Tracing circuits are disposed within each node circuit in a mesh network to debug problems found during development. The tracing circuit disclosed includes a trace read interface for accessing trace packets stored in a trace buffer at entries that are mapped to system memory addresses. Processing circuits coupled to the trace read interface may access the stored trace packets using memory instructions. The trace packets include trace information generated from packets that are detected on selected ports of a node circuit in a node of the mesh network. A filter circuit compares the transaction units to a trace criteria and stores the trace information of the matching packets in the form of trace packets in the memory-mapped entries of the trace buffer. The trace packets can include the transaction units of a packet or just packet header information for more efficient use of the trace buffer.
Bibliography:Application Number: US202318528225